1. Field of the Invention
The present invention relates to clear processing of a translation lookaside buffer (TLB), and more particularly, to a method and apparatus for clear processing of a TLB with less waiting time.
2. Description of the Related Art
In a conventional computer system a TLB clear control system is employed to speed up the processing. The conventional TLB clear control system of a multiprocessor system is shown in FIG. 1. The multiprocessor system includes a plurality of processors P101 to P10n, a main memory 2 and a flag F3. Each processor includes an executing section 131-i (i=1 to n) and a TLB 132-i. The flag F3 indicates that a TLB clear request is not allowed to be issued when it is set and that the TLB clear request is allowed to be issued when it is reset.
When one of the plurality of processor, for example, a processor P101 intends to execute an instruction requiring to clear its own TLB, the executing section 131-1 of the processor P101 refers to the flag F3 to see whether or not a TLB clear request is allowed to be issued. When the TLB clear request is not allowed to be issued, the executing section 131-1 waits until the flag F3 is reset, i.e., until the issuing of the TLB clear request is allowed. When the TLB clear request is allowed to be issued, the executing section 131-1 sets the flag F3 and then issues the TLB clear requests to the processors other than the issuing processor P101 in the multiprocessor system. Thereafter, the processor P101 waits for TLB clear processing end notices from all the other processors. When the executing section 131-1 receives the TLB clear processing end notices, it resets the flag F3 and then executes the above instruction.
On the other hand, the processor P101 performs the TLB clear processing for its own TLB 132-1 in response to the TLB clear request issued from another processor, after the executing section 131-1 has executed an instruction or while the processor P101 waits for the TLB clear processing end notices from the other processors for the TLB clear request issued from the processor P101. When performing the TLB clear processing, the executing section 131-1 issues a TLB clear processing end notice to the other processor which has issued the TLB clear request.
In this manner, in the conventional multiprocessor system having a plurality of processors each of which includes a TLB, there is a problem in that when a processor intends to clear the TLB for storing address translation information, after issuing a TLB clear request, the processor needs to wait for TLB clear processing end notices from all the other processors to maintain the coincidency of contents of the TLBs in all the processors.
Also, when the processor receives TLB clear requests issued by processors other than itself, the processor sequentially processes the TLB clear requests one by one. Therefore, there is another problem in that the other processors need to wait until the TLB clear requests issued from the processors are processed.
Further, the time required to perform the TLB clear processing is elongated as the number of processors in a multiprocessor system increases, resulting in the degradation of processing capability in the multiprocessor system.